Conventionally, an automatic gain control (AGC) circuit is used as a constituent element of a transimpedance amplifier circuit that converts a small photocurrent into a voltage signal and simultaneously amplifies it. FIG. 12 shows the arrangement of a transimpedance amplifier circuit disclosed in literature “Kimikazu Sano, et al., “A Wideband Low-distorted ROSA for Video Distribution Service based on FM Conversion Scheme”, ECOC 2007 Proceedings, Vol. 3, pp. 167-168, 2007”.
A transimpedance core circuit 1 converts a current signal obtained by a light-receiving element such as a photodiode (not shown) into a voltage signal. An offset compensator circuit 2 compensates for the offset from the output signal of the transimpedance core circuit 1. A variable gain amplifier 3 amplifies the output signal from the transimpedance core circuit 1. The output signal from the variable gain amplifier 3 is output to differential output terminals OT and OC via an output buffer 4. An automatic gain control circuit 5 generates a gain control signal and controls the gain of the variable gain amplifier 3 such that the amplitude of the output signal of the variable gain amplifier 3 matches a predetermined set output amplitude.
The automatic gain control circuit 5 will be described below in detail. The automatic gain control circuit 5 includes a peak detector circuit 50, an average value detector circuit 51, an output amplitude setting circuit 52, an operational amplifier 53, resistors r51, r52, r53, and r54, and capacitors c51, c52, and c53. The peak detector circuit 50 detects a peak value THo of the output signal from the variable gain amplifier 3. The average value detector circuit 51 detects an average value Ave of the output signals from the variable gain amplifier 3. The difference between the peak value THo and the average value Ave corresponds to the half (half amplitude) of the amplitude of the output signal from the variable gain amplifier 3. A set output half amplitude Aset to be used as a reference is set in the output amplitude setting circuit 52 in advance. The output amplitude setting circuit 52 outputs the set output half amplitude Aset to the noninverting input terminal and the inverting input terminal of the operational amplifier 53.
At the input of the operational amplifier 53, the output amplitude of the variable gain amplifier 3 and the set output half amplitude Aset output from the output amplitude setting circuit 52 are added as indicated byAve−THo+ASet  (1)At the time of stable operation, the input to the operational amplifier 53 is almost 0 because of the high gain properties of the operational amplifier itself. For this reason, the value of expression (1) is almost 0, that is,THo−Ave≈ASet  (2)holds.
That is, the operational amplifier 53 amplifies the difference between the set output half amplitude Aset and the output half amplitude (THo−Ave) of the variable gain amplifier 3, and outputs the gain control signal to the variable gain amplifier 3 based on the amplification result. The operational amplifier 53 thus controls the gain of the variable gain amplifier 3 such that the output half amplitude (THo−Ave) of the variable gain amplifier 3 stabilizes in the set output half amplitude Aset.
As the variable gain amplifier 3, for example, a Gilbert cell type variable gain amplifier is used. FIG. 13 shows the arrangement of a Gilbert cell type variable gain amplifier disclosed in literature “P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer (authors); Kunihiro Asada and Minoru Nagata (supervisors of translation), “Analysis and Design of Analog Integrated Circuits”, fourth edition, Baifukan, pp. 263-264, 2003”. This variable gain amplifier includes amplitude adjustment transistors Q30 and Q31 forming an upper differential pair for adjusting the output amplitude in accordance with gain control signals GCT and GCC input to the bases, amplitude adjustment transistors Q32 and Q33 forming another upper differential pair, amplification transistors Q34 and Q35 having bases connected to a positive-phase input terminal HIT and a negative-phase input terminal HIC, respectively, and forming a lower differential pair, a current source I30 having one terminal connected to the emitters of the amplification transistors Q34 and Q35 and the other terminal receiving a power supply voltage VEE, a collector resistor R30 having one terminal receiving a power supply voltage VCC and the other terminal connected to the collectors of the amplitude adjustment transistors Q30 and Q32, and a collector resistor R31 having one terminal receiving the power supply voltage VCC and the other terminal connected to the collectors of the amplitude adjustment transistors Q31 and Q33. The collector of the amplification transistor Q34 is connected to the emitters of the amplitude adjustment transistors Q30 and Q31. The collector of the amplification transistor Q35 is connected to the emitters of the amplitude adjustment transistors Q32 and Q33.
In the variable gain amplifier shown in FIG. 13, the positive-phase input signal and the negative-phase input signal output from the transimpedance core circuit 1 are input to the positive-phase input terminal HIT and the negative-phase input terminal HIC, respectively. The gain control signals GCT and GCC are input to the amplitude adjustment transistors Q30 and Q31 forming an upper differential pair, respectively. The gain control signals GCT and GCC are also input to the amplitude adjustment transistors Q33 and Q32 forming another upper differential pair, respectively. The node between the collector resistor R31 and the collectors of the amplitude adjustment transistors Q31 and Q33 is connected to a positive-phase output terminal HOT. The node between the collector resistor R30 and the collectors of the amplitude adjustment transistors Q30 and Q32 is connected to a negative-phase output terminal HOC.